1. Field of the Invention
The present invention relates generally to a unit semiconductor chip, semiconductor package and methods for manufacturing the same. More particularly, the present invention relates to a unit semiconductor chip and a stacked semiconductor package having semiconductor chips with center bonding pads and methods for manufacturing the same.
2. Description of Related Art
As a result of developments in semiconductor technology and user demands, the electronic industry has been engaged in continuing efforts to reduce the size, thickness and power consumption of semiconductor devices. In order to meet the requirement of the electronic industry, semiconductor devices are becoming more highly integrated. A conventional semiconductor package using solder balls instead of connecting pins is a ball grid array (BGA) package and a conventional packaging process have been generally for integrated semiconductor packages, such as chip scale packages (CSPs).
Demand for compact semiconductor devices with larger capacity has resulted in the development of stacked semiconductor packages. In general, stacked semiconductor packages have been adopted because of the possibility of easily increasing the memory capacity of a semiconductor package by two or more, by stacking two or more packages.
FIG. 1 is a cross-sectional view of a conventional BGA package 10 having a semiconductor chip 20 with center bonding pads 25. As illustrated in FIG. 1, the conventional BGA package 10 including a semiconductor chip 20 with center bonding pads 25 may include a printed circuit board 11 including wiring patterns 13 formed on the peripheral area of the printed circuit board 11. The semiconductor chip 20 with the center bonding pads 25 may be attached on a top side of the printed circuit board 11 by an adhesive layer 30. An insulating layer 28 may be formed in order to protect a circuit layer (not shown) on the semiconductor chip 20. The center bonding pads 25 and the wiring patterns 13 may be electrically connected by bonding wires 35. The semiconductor chip 20 and the bonding wires 35 may be sealed by an encapsulation 40. A plurality of solder ball pads 50 may be formed on the underside of the printed circuit board 11 and solder balls 55 may be attached corresponding to the plurality of solder ball pads 50. The solder balls 55 may be electrically connected to the wiring patterns 13 of the printed circuit board 11.
As described above, the conventional BGA package 10 may decrease a mounting density when connected to a mother board (not shown), as a result of using the printed circuit board 11, instead of a lead frame and using the solder balls 14 as external connection terminals. However, the conventional BGA package 10 including the semiconductor chip 20 with center bonding pads 25 has longer bonding wires 35 connecting the center bonding pads 25 and the wiring patterns 13 than semiconductor chips with edge pads. Further, electrical failures may occur between an edge portion of the semiconductor chip 20 and the bonding wires 36, as a result of reducing the height of the wire loop to reduce the overall thickness of the package. Furthermore, the conventional stacking process of manufacturing such a stacked semiconductor package may be difficult, as a result of sealing the top surface of the semiconductor chip 20 with the center bonding pads 25.